Instruction Format

Composition of Instruction

Operation Code (Op code): Tell CPU what to do.
Operands: Tell CPU the content of doing action, including source operand and destination operand.

Three-address Instruction and Two-address Instruction: General-purpose register machine.
One-address Instruction: Accumulator-based machine.
Zero-address Instruction: Stack machine.

| 7 6 | 5 4 3 | 2 1 0 |
  MOD    REG     R/M

MOD Meaning

00

`R/M`	Operation
`100`	SIB
`110`	Memory direct addressing mode (Displacement only addressing mode) (16-bit displacement)
`101`	Memory direct addressing mode (Displacement only addressing mode) (32-bit displacement)
Other	Register indirect addressing mode with no displacement

01 One-byte signed displacement follows addressing bytes

10 Four-byte signed displacement follows addressing bytes

11 Register addressing mode

REG Value	Register (8-bits)	Register (16-bits)	Register (32-bits)
`000`	`AL`	`AX`	`EAX`
`001`	`CL`	`CX`	`ECX`
`010`	`DL`	`DX`	`EDX`
`011`	`BL`	`BX`	`EBX`
`100`	`AH`	`SP`	`ESP`
`101`	`CH`	`BP`	`EBP`
`110`	`DH`	`SI`	`ESI`
`111`	`BH`	`DI`	`EDI`

Last updated on May 31, 2026