Digital Components

Logic Gates

Name	Graph	Formula
AND		$F = A \cdot B$
OR		$F = A + B$
NOT		$F = \overline{A}$
NAND		$F = \overline{AB}$
NOR		$F = \overline{A + B}$
XOR		$F = A \oplus B$

Decoder

An $n \times 2^n$ decoder has $n$ binary coded inputs and $2^n$ outputs.

Usually, if $n$ inputs are treated as binary code, which means that $n = (c_{n-1}c_{n-2}\dots c_0)_{2}$, and the outputs are $m_0, m_1, \dots, m_{n-1}$, then we have:

$$m_i = 1 \Longleftrightarrow i = (c_{n-1}c_{n-2}\dots c_0)_{2}$$

$3 \times 8$ Decoder

This decoder combines AND and NOT gates together.

In addition, there are two enable controllers controlling whether to enable a gate.

Encoder

A $2^n \times n$ encoder has $2^n$ inputs and $n$ binary coded outputs.

The encoder and decoder perform opposite operations.

In addition, there are $2^n$ inputs in an encoder, but there is only one input can be turned on at one time to ensure the output is unique.

$8 \times 3$ Decoder

The encoder only has OR gate.

The v stands for valid, which is used to determine whether the input is valid. When all inputs are 0, then the output is invalid or do not care, which will be $0$.

Multiplexer

A $2^n \times 1$ multiplexer has $2^n$ data inputs, $n$ control inputs, and one or two outputs.

The $n$ control inputs determine which inputs are valid, playing a function of selecting.

$4 \times 1$ MUX

The inner structure of a $4 \times 1$ MUX is as following.

And it can be encapulated as:

The selectors (or control inputs) can be treated as binary codes, and input $d_i \;,\; i \in [0, 4)$ is activated when $i = (s_1 s_0)_2$.

$4 \times 1$ multiplexers can be combined to form other multiplexers like $8 \times 1$ MUX: