Basic Computer Organization

Stored Program Organization

A stored-program digit computer is one that keeps its programmed instructions, as well as its data, in read-write, random access memory (RAM).

The von Neumann architecture is a design model for a stored-program digit computer that uses a processing unit and a single separate storage structure to hold both instructions and data.

The organization diagram looks like:

Timing and Control

Clock

Activities including reading from memory or I/O and writing to memory I/O, on the system bus is synchronized by the system clock.

Clock cycle determines the speed of a computer processor or a CPU.

The clock speed is measured in Hz, typically either megahertz (MHz) or gigahertz (GHz).

One complete cycle is called as T-state.

Bus Cycle

Any read or write cycle is called a bus cycle or machine cycle.

In 8086, a bus cycle takes $4T$ states.

During a machine cycle, one specific operation, reading or writing, is accomplished.

There are 4 basic machine cycles:

• Memory Read
• Memory Write
• I/O Read
• I/O Write

Instruction Cycle

It is time taken by processor to execute an instruction.

Once an instruction is fetched and ready to be executed, then it can be decoded and execution can be set.

The fetch-execute cycle can be divided into 6 stages:

1. Fetch instruction.
   • The next instruction is fetched from the memory address stored in the program counter (PC) and in the instruction register (IR).
   • After the fetch operation, the PC points to the next instruction that well be read at the next cycle.
2. Decode instruction.
   • The encoded instruction presented in the IR is interpreted by the decoder.
3. Read operand address.
4. Fetch operand.
5. Execute instruction.
6. Write/store result in memory.

Chip Organization

• Hardware
  • PC / Workstation / Mainframe
  • Network
• Software
  • Operating Systems
  • Program: A set of instructions for a computer to follow.

  graph TD
    p["Program"]
    d["Data"]
    c["Computer"]
    o["Output"]

    p --> c
    d --> c
    c --> o

Von Neumann Computer Model

There are five main components in a computer.

Central Processing Unit (CPU)

It is an electronic circuitry that carries out the instruction given by a computer program.

It executes instruction by performing basic arithmetic, logic, control, and I/O operations as required per instruction.

Main Memory

It is random access memory (RAM), used when running the program.

Secondary Memory

It includes Hard disks, CD / DVD flash drives, and data storage for permanent record.

Input Devices

They allow a person to communicate information to the computer, including keyboard, mouse, microphone, camera, etc.

Output Devices

They allow a computer to communicate information to the users, including monitor, speaker, printer, etc.

Important Terminologies

  graph LR
    mcs["Microcomputer System"]
    mcs --> hw["Hardware"]
    mcs --> sw["Software"]

    hw --> mc["Microcomputer"]
    hw --> pe["Peripheral Equipment"]

    mc --> mp["Microprocessor"]
    mc --> mrr["Memory (RAM / ROM)"]
    mc --> iop["I/O Port"]
    mc --> bus["Bus (AB, DB, CB)"]

    mp --> alu["ALU"]
    mp --> reg["Register"]
    mp --> cop["Contrl Part"]

    pe --> ext["External"]
    pe --> aup["Auxiliary Part"]

    ext --> id["Input Device"]
    ext --> od["Output Device"]

    aup --> powc["Power Circuit"]
    aup --> cloc["Clock Circuit"]

    sw --> ss["System Software (Operating System, Compile Programmer, etc.)"]
    sw --> ps["Programming Software (Machine Language, Assemble Language, etc.)"]
    sw --> ap["Application Software (Data Processing, Industrial Control, etc.)"]

I/O and Interrupt

Interrupt is the method of creating a temporary halt during program execution, and allows peripheral devices to access the microprocessor.

And the microprocessor responds to that interrupt with an ISR (Interrupt Service Routine), which is a short program to instruct the microprocessor on how to handle the interrupt.

Types of Interrupts

  graph TD
    it["Interrupts"]

    it --> hi["Hardware Interrupt"]
    it --> si["Software Interrupt"]

    hi --> mi["Maskable Interrupt"]
    hi --> nmi["Non-Maskable Interrupt"]

Hardware Interrupts

It is caused by any peripheral device by sending a single through a specific pin to the microprocessor.

The 8086 has two hardware interrupt pins, which are NMI and INTR.

NMI

It is a non-maskable interrupt with higher priority, and it is of type 2 interrupt. Actions will be taken when it is activated:

1. Completes the current instruction that is in progress.
2. Push the flag register values onto the stack.
3. Pushes the CS (code segment) value and IP (instruction pointer) value of the return address on to the stack.
4. IP is loaded from the contents of the word location 00008H.
5. CS is loaded from the contents of the next word location 000AH.
6. Interrupt flag and trap flag are reset to 0.

INTR

It is a maskable interrupt with lower priority, because the microprocessor will be interrupted only if interrupts are enabled by setting interrupt flag instruction.

The INTR interrupt is activated by an I/O port. If the interrupt is enabled and NMI is disabled, then the microprocessor first completes current execution and sends $0$ on INTR pin twice, where the first $0$ means that INTR informs the external device to get ready and during the second $0$ the microprocessor recives the $8$ bit, say $X$, from the programable interrupt controller.

The process of enabling INTR is:

1. First completes the current instruction.
2. Activates INTR output and receives the interrupt type, say $X$.
3. Flag register value, CS value of the return address and IP value of the return address are pushed on to the stack.
4. IP value is loaded from the contents of word location $X \times 4$
5. CS is loaded from the contents of the next word location.
6. Interrupt flag and trap flag is reset to $0$.