General Register Organization

Three Types of CPU Organization

• Single accumulator organization: Like basic computer design.
• General register organization: a set of general registers to store data.
• Stack organization.

Functions of CPU

• Control all other parts of the machine and sending timing signals.
• Transfer data between memory and I/O devices.
• Fetch data and instructions from memory.
• Decode instruction.
• Perform arithmetical and logical operations.
• Execute programs stored in memory.
• Communicate among I/O devices.

CPU-8086

Execution Unit (EU) is responsible for decoding and executing instructions.

Bus interface unit (BIU) is responsible for performing all external bus.

Execution Unit (EU)

Functions

• Tell BIU regarding from where to fetch instructions or to read data.
• Receives opcode of an instruction from the queue.
• Decode the instructions.
• Execute the instructions.

Components

• General purpose registers: Used to store temporary data.
• Stack pointer
• Base pointer
• Index and pointer registers: Specify / Inform about offset of operand.
• ALU: Perform arithmetic and logical operations.
• Flag register (FLAGS / PSW): Reflect the status of program.
• Instruction decoder: Translate instructions fetched from memory into series of actions.
• Timing and control unit
• Control circuitry: Direct internal operations.

Bus interface unit (BIU)

Functions

• Handle transfer of data and address between processor and memory or I/O devices.
• Compute physical address and send it to memory interfaces.
• Fetch instruction codes and store them in queue.
• Read/Write data from/to memory or I/O devices.
• Relocate the addresses of operands sent by EU.

Components

• Segment register: Used to hold the starting address of segment.
• Instruction pointer: Used to point to the next instruction to be executed by EU.
• Address generation adder: Compute physical address and send it to memory interfaces.
• Instruction queue: Used to store prefetched instructions and input it to EU.
• Bus control logic

Process

  graph LR
    mio["Memory & I/O"] <--> biu

    subgraph " "
        cs["CS: IP: 20-bit physical address"]
        biu["BIU: fetch the instruction and wait in instruction array"]
        eu["EU: decode the instruction"]

        cs-->biu-->eu-->cs
    end